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Title:
MASTER/SLAVE FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JPS5580914
Kind Code:
A
Abstract:

PURPOSE: To obtain a master/slave flip-flop MSFF which features a small number of the element and is suited to formation of the integration.

CONSTITUTION: Master MFF is formed by securing the cross connection between transistor TrQ1 and Q2. Diodes D1 and D2 are for level shift. At the same time, TRQ2, Q3, Q5 and Q6 form slave SFF. And no inverter is inserted between MFF and SFF especially. In such constitution, the function is given so that the MFF and SFF are isolated from each other when the clock pulse is at a high level and that they are connected to each other when the clock pulse is at a low level respectively. Thus the number can be reduced greatly for the elements necessary to form the 1- step MSFF, which can be suited to be used as the unit circuit of the shift register in case the monolithic integration is formed.


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Inventors:
SATOU HIROAKI
Application Number:
JP15531478A
Publication Date:
June 18, 1980
Filing Date:
December 14, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K3/289; H03K3/037; (IPC1-7): H03K3/289



 
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