Title:
FLIP-FLOP, SHIFT REGISTER, AND ACTIVE MATRIX TYPE DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2005244956
Kind Code:
A
Abstract:
To improve both of rising characteristics and falling characteristics of an output signal in a flip-flop, and to reduce the signal delay of a shift register constituted by this flip-flop.
A latch unit 22 has a latch circuit for latching a signal inputted from a gating unit 21 configured by an inverter 24 and an inverter 25, and an analog switch ASW2 for switching an on/off state, in response to a High/Low state of a reset signal R is disposed between the inverter 24 of the latch circuit and an output terminal OUT. A switching element Mn6 for switching the on/off state, according to the High/Low state of the reset signal between an input of a low potential VSS of an operating power source of the flip-flop and the output terminal OUT.
Inventors:
WASHIO HAJIME
MURAKAMI YUICHIRO
BROWNLOW MICHAEL JAMES
MURAKAMI YUICHIRO
BROWNLOW MICHAEL JAMES
Application Number:
JP2005017432A
Publication Date:
September 08, 2005
Filing Date:
January 25, 2005
Export Citation:
Assignee:
SHARP KK
International Classes:
G02F1/133; G09G3/20; G09G3/30; G09G3/36; G11C11/412; G11C19/00; H03K3/012; H03K3/037; H03K3/356; H03K23/00; (IPC1-7): H03K3/356; G02F1/133; G09G3/20; G09G3/36; G11C11/412; G11C19/00; H03K3/037; H03K23/00
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
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