PURPOSE: To attain high speed operation by shifting a DC level of a clock fed to a base of the 3rd transistor (TR) to the level higher than the DC level of the data fed to the base of the 1st and 2nd TRs higher by nearly a 1/2 level of the logical amplitude.

CONSTITUTION: TRs 3, 8 are turned on at a clock high level, TRs 1, 2 and 2, 7 are turned off, a current flows to a latch circuit connected to the collector of the TRs 3, 8 to attain latch operation. The TRs 3, 8 are turned off at the low level of the clock, a TR having a high level data fed to the base in the TRs 1, 6 and 2, 7 is turned on to attain level comparison.