Title:
浮遊ゲートアナログ回路
Document Type and Number:
Japanese Patent JP2005522071
Kind Code:
A
Abstract:
In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or more of several matrix modes. A few examples of such matrix modes include a switching matrix mode, a memory matrix mode, and a computing matrix mode. In an exemplary method of configuring the PAA. PAA, the the method includes programming an interconnection, for example, between a first terminal of the first floating-gate FET and a first terminal of the second floating-gate FET. The method further includes programming an interconnection, for example, between a gate terminal of the first floating-gate FET and a fixed voltage source, for setting a floating gate charge on the first floating-gate FET.
Inventors:
Hall, Tyson, S.
Hustler, Paul
Anderson, David, Vee.
Smith, Paul, Dee.
Kushik, Matthew, Raymond
Brown, Edgar, Alejandro
Hustler, Paul
Anderson, David, Vee.
Smith, Paul, Dee.
Kushik, Matthew, Raymond
Brown, Edgar, Alejandro
Application Number:
JP2003579409A
Publication Date:
July 21, 2005
Filing Date:
March 24, 2003
Export Citation:
Assignee:
Georgia Tech Research Corporation
International Classes:
G11C27/00; G06G7/12; H01L21/82; H01L21/8247; H01L27/115; H01L29/76; H01L29/788; H01L29/792; H03F1/32; H03F3/08; H03F3/45; H03K19/177; H04L; (IPC1-7): H03K19/177; G11C27/00; H01L21/82; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Katsuichi Nishimoto
Kato Kazunori
Katsuichi Nishimoto