PURPOSE: To perform the addition or subtraction calculation of a floating point with a little hardware amount at high speed.

CONSTITUTION: Mantissa part data MC' is imparted to an inversion circuit 7 and a selector 9. The output of the inversion circuit 7 and the output of a left shifter 14 are imparted to a selector 30. When a borrow output is '1' and the mantissa part data MC' is made the complement display of 2, the output of the inversion circuit 7 is imparted to an incrementer 31 via the selector 30 and the mantissa part data of an absolute value display is imparted to a shift control circuit 13. When the borrow output is '1', the selector 9 imparts the mantissa part data MC' as it is to a shift control circuit 13. In order to perform a rounding processing for the mantissa part data MC', the selector 30 imparts the output of the left shifter 14 to the incrementer 31 and a selector 17 selects the output of the incrementer 31. Therefore, the incrementer 31 is used in the both of the conversion from the complement display to the absolute value display and the rounding processing.