FLOATING-POINT ARITHMETIC UNIT

Japanese Patent JP3600026

B2

PROBLEM TO BE SOLVED: To obtain a floating-point arithmetic unit which reduces the critical path of accumulation processing in the interation execution of continued product- sum operations and accomplishes the reduction of operation time by starting to execute the calculation of a digit place matching number necessary for a product-sum operation to be next carried out in parallel with normalization processing before completing the normalization processing of the preceding product-sum operation.
SOLUTION: The configuration of an adder 3 and registers 4 and 5 is added to an adding part 2, an output of a selector 212 is given to one input of an adder 210 and an adder 3 calculates a digit place matching number S by adding the addition results of the adder 210 to a normalizing number N obtained by a precedent 0 detection circuit 204. That is, the adder 3 calculates the digit place matching number S for subsequent product-sum operations before finishing the normalization of the current product-sum operation. The calculated digit matching number S is stored by a register 5, a shifter 201 is subjected to shift control by the stored digit place matching number S, the carry of the addition results of the adder 3 is stored by the register 4 and the selector 212 and a swap operation are controlled.

Susumu Ide

JP22826798A

December 08, 2004

August 12, 1998

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Toshiba Corporation

G06F7/00; G06F5/01; G06F7/544; G06F7/76; G06F9/302; G06F17/10; (IPC1-7): G06F17/10; G06F5/01; G06F7/00

JP10207863A
JP9507941A
JP9212482A
JP8087399A
JP7114455A
JP62196767A

Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio

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