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Patent Searching and Data


Title:
FLOATING POINT ADDITION/SUBTRACTION DEVICE
Document Type and Number:
Japanese Patent JP01128129
Kind Code:
A
Abstract:

PURPOSE: To carry out the substantial subtraction at a high speed by producing and holding the N-byte carry production and transmission conditions, obtaining and holding all N-byte initial carries via a carry farseeing circuit, and selecting the initial carry via a selector.

CONSTITUTION: The expanding accuracy addition/subtraction instructions carry out successively the arithmetic process for the high order data setting, the low order data setting, the low order data addition/subtraction, the low order data addition/subtraction, the high order data result output, and the low order data result output respectively. A condition production circuit 62 obtains the high order (M-1) pieces of N-byte carry production and transmission conditions and holds them in registers 70 and 71 before the least significant digit N-byte addition/subtraction. At execution of the addition/subtraction a carry farseeing circuit 80 obtains all N-byte initial carries and holds them in a register 81. A selector 82 selects the initial carry and supplies successively the high order N-type arithmetic data for execution of the addition/subtraction operations to obtain M pieces of addition/subtraction results. Thus it is possible to perform the substantial subtraction with an expanding accuracy addition/subtraction instruction.


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Inventors:
Takiguchi, Makoto
Hiyama, Koichi
Watanabe, Takeshi
Application Number:
JP1987000286774
Publication Date:
May 19, 1989
Filing Date:
November 13, 1987
Export Citation:
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Assignee:
HITACHI LTD
HITACHI COMPUT ENG CORP LTD
International Classes:
G06F7/50; G06F7/483; G06F7/508; G06F7/48; (IPC1-7): G06F7/50