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Patent Searching and Data


Title:
FORECASTING CODING CIRCUIT
Document Type and Number:
Japanese Patent JPS6041892
Kind Code:
A
Abstract:

PURPOSE: To give a margin to delay time of a critical path by delaying clock input of a final stage register of the criticsal path and replacing order if arithmetic of succeeding limiter and register.

CONSTITUTION: The forecasting coding circuit consists of an inside differential circuit B, an outside differential circuit A and a quantizer 5. The critical path 22 of the forecasting coding circuit is a path starting from a register 4 and going to a register 9 through the quantizer 5 and adders 6, 8. Clock input of the register 9 is delayed from clock input of the register 4 by a delay circuit 21. Accordingly, delay time of the critical path can be taken longer than 1 time slot and margin is increased. However, it becomes necessary to shorten the signal path that follows the critical path. Order of arithmetic of the limiter 10 and a register 11 is interchanged for this purpose.


Inventors:
CHIYOU FUJIO
Application Number:
JP14988183A
Publication Date:
March 05, 1985
Filing Date:
August 17, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03M7/32; H04N11/04; (IPC1-7): H03M7/32; H04N7/13; H04N11/04
Attorney, Agent or Firm:
Uchihara Shin