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Title:
FORECASTING PARITY GENERATION SYSTEM OF REGISTER
Document Type and Number:
Japanese Patent JPS5762445
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of a register with simple constitution by inverting a JKFF for a check bit when detecting an input signal changing by odd-numbered bits, by using a prescribed number of output bits of the JKFF and the input signal.

CONSTITUTION: An n-bit register is composed of J-KFF1WJ-KFFn, and a JKFFP for a check bit is further added. Then, set and reset input signals ST1WSTn, and RS1WRSn are inputted to the FF1WFFn and when the number of bits changing from their last states is found odd-numbered through AND circuits A11, A12WAn1, and An2 and a parity generator PG by output bits B1WBn and input signals ST1WSTn, and RS1WRSn, the parity bit Bp of the output of the FFP is inverted. Consequently, data having an added parity bit is transferred to a circuit following the register, whose reliability is improved.


Inventors:
SATOU SHINICHI
Application Number:
JP13836980A
Publication Date:
April 15, 1982
Filing Date:
October 03, 1980
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/10; H03M13/00; (IPC1-7): G06F11/10