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Title:
FORMATION OF FINE METALLIC PATTERN BY DAMASCENE TECHNIQUE
Document Type and Number:
Japanese Patent JP3932345
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a method for forming a fine metallic pattern of a semiconductor element, based on a damascene technique which can ensure broad width of a metallic layer for improving the operational speed of the element and can easily control steps by etching only the metal layer without etching the metallic layer, anti-diffusion layer and bonding layer at the same time.
SOLUTION: This method includes a first step of sequentially forming a glue layer 21 and an anti-diffusion layer 22, a second step of forming an insulating film pattern defining a fine pattern region on the anti-diffusion layer 22, a third step of forming a metallic layer 25 on the fine pattern region, a fourth step of forming an etching stop layer on the metallic layer 25, a fifth step of removing the insulating film pattern to expose the anti-diffusion layer 22, and a sixth step of selectively etching the anti-diffusion and glue layers 22 and 21 respectively with the use of the etch stop layer as an etching mask.


Inventors:
Youn Hi Ryu
Long-growing root
Application Number:
JP34687699A
Publication Date:
June 20, 2007
Filing Date:
December 06, 1999
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/3205; H01L21/3213; H01L21/28; H01L21/60; H01L21/768; (IPC1-7): H01L21/3213
Domestic Patent References:
JP2162728A
JP6120212A
JP1208842A
Attorney, Agent or Firm:
Kyosei International Patent Office