Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FORMATION OF GATE ELECTRODE
Document Type and Number:
Japanese Patent JPS6414968
Kind Code:
A
Abstract:

PURPOSE: To improve the breakdown strength of the device as well as to improve its reliability by a method wherein an amorphous silicon layer and a polycrystalline silicon layer are laminated successively on the surface of a gate insulating film, and the gate electrode having a smooth surface is obtained by conducting selective etching on said two silicon layers.

CONSTITUTION: A gate insulating film 3 is formed by selectively providing a field insulating film 2 on the surface of a one-conductive type silicon substrate 1. Then, an amorphous silicon layer 4, containing oxygen of 1∼20 atomic % is formed on the gate insulating film 3 by conducting a thermal decomposition method at the pressure of 0.5Torr and at the temperature of 600°C using the mixture of silane gas and nitrous oxide gas. Then, a polycrystalline silicon layer 5 of 0.5μm in thickness is deposited on the layer 4 by conducting a silane gas thermal decomposition method at the pressure of 0.5Torr and at the temperature of 640°C without exposing the surface of the amorphous silicon layer 4. A gate electrode is formed on the above-mentioned element formation region by conducting selective etching sucessively on the polycrystalline silicon layers 5 and the amorphous silicon layer 4.


Inventors:
OGAWA KICHIJI
Application Number:
JP17150187A
Publication Date:
January 19, 1989
Filing Date:
July 08, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H01L29/78; (IPC1-7): H01L29/78
Domestic Patent References:
JPS63255972A1988-10-24
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)