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Title:
FORMATION OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0715015
Kind Code:
A
Abstract:
PURPOSE: To prevent a latch-up and to increase the breakdown voltage by implanting neutral impurity ions into a silicon transistor element. CONSTITUTION: An element 10 has a substrate 12, a buried insulating oxide 14, a drain region 16 and a source region 18. A main body region 24 is a channel region under a gate between the source region and the drain region of the element. In a treatment operation, an annealing treatment is performed after neutral species are implanted to remove a damage caused by implantation. Since the neutral impurities include VIII group atoms such as krypton, xenon, germanium and the atoms are large in size and cause turbulence in a band structure, the scattering centers to high energy carriers in a transistor increases. When a drain field having a neutral impurity center is constant, a collision ionization current decreases and a parasitic bipolar effect also decreases, which can prevent a latch-up and increase the breakdown voltage.

Inventors:
FUREDERITSUKU TEI BURADEI
NADEIMU EFU HADATSUDO
AASAA EDENFUERUDO
Application Number:
JP7865494A
Publication Date:
January 17, 1995
Filing Date:
April 18, 1994
Export Citation:
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Assignee:
INTERNATL BUSINESS MACH CORP
International Classes:
H01L29/78; H01L21/265; H01L21/336; H01L27/08; H01L27/12; H01L29/786; (IPC1-7): H01L29/786; H01L21/336
Domestic Patent References:
JPH03119732A1991-05-22
JPH04337625A1992-11-25
Attorney, Agent or Firm:
合田 潔 (外2名)



 
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