Title:
FORMATION OF LAYOUT OF PATTERN FOR LSI, FORMATION OF PATTERN FOR LSI AND FORMATION OF MASK DATA FOR LSI
Document Type and Number:
Japanese Patent JP3482172
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make it possible to surely execute the proximity effect correction capable of forming a circuit pattern to enable operation while subjecting an LSI(large-scale integrated circuit) to desired fining.
SOLUTION: This method for formation of a layout consists in first setting a design rule, basic process conditions, etc., (SB1). Next circuit patterns are formed in accordance with the set design rule (SB2) and thereafter, whether the formed circuit patterns satisfy the design rule or not is certified (SB3). OPC (proximity effect correction) pattern forming specifications are then set (SB5) and the OPC patterns are formed from the respective circuit patterns in accordance with the OPC pattern forming specifications (SB6). Whether the formed OPC patterns satisfy an OPC pattern arrangement rule or not is certified (SB7). Whether an OPC effect may be obtained or not is certified (SB10). If the OPC pattern arrangement making it infeasible to obtain the OPC effect is decided to exist (SB11), the design rule is so corrected as not to generate the OPC pattern arrangement making it infeasible to obtain the OPC effect (SB12).
Inventors:
Akio Misaka
Shinji Odanaka
Shinji Odanaka
Application Number:
JP2000048766A
Publication Date:
December 22, 2003
Filing Date:
February 25, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/027; G03F1/36; G03F1/68; G03F1/70; G06F17/50; (IPC1-7): G03F1/08; G06F17/50; H01L21/027
Domestic Patent References:
| JP9319067A | ||||
| JP876348A |
Attorney, Agent or Firm:
Hiroshi Maeda (1 person outside)