Title:
FORMATION OF METAL SILICIDE LAYER
Document Type and Number:
Japanese Patent JP3394927
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for forming a low resistance metal silicide layer easily on a substrate while suppressing consumption of Si.
SOLUTION: The method for forming a metal silicide layer comprises a step for forming a first metal layer 14 by depositing a first metal on a region 12 containing Si, a step for forming a second metal layer 16 by depositing a second metal on the first metal layer, a step for forming an antioxidation layer 18 on the second metal layer, a step for forming a metal silicide layer 20 from the region containing Si on the first metal layer side and the region of the first metal layer on the side of the region containing Si by heat treating a structure including the region containing Si, the first metal layer, the second metal layer and the antioxidation layer, and also forming an alloy layer 22 containing the first and second metals from the region of the first metal layer on the second metal layer side and the second metal layer, a step for removing the antioxidation layer and then a part 14x of the first metal layer and the alloy layer, and a step for changing a metal silicide preliminary layer into a metal silicide layer 20x by heat treating the metal silicide preliminary layer at a temperature higher than that of the first heat treatment.
Inventors:
Kaori Tai
Application Number:
JP18315299A
Publication Date:
April 07, 2003
Filing Date:
June 29, 1999
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H01L29/78; H01L21/28; H01L21/285; H01L21/336; (IPC1-7): H01L21/28; H01L21/336; H01L29/78
Attorney, Agent or Firm:
Takashi Ogaki