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Title:
FORMATION METHOD OF MIS STRUCTURE ELECTRODE
Document Type and Number:
Japanese Patent JPH0491436
Kind Code:
A
Abstract:

PURPOSE: To obtain a MIS structure electrode which reduces an interface level density and whose characteristic is excellent by a method wherein, before an insulating film is formed, a sulfur passivation treatment is executed to the surface of a substrate and the insulating film is formed by an ECR-CVD method.

CONSTITUTION: An insulating film 14 is formed on a substrate 11 composed of a III-V compound semiconductor; after that, an electrode material is applied to form a MIS structure electrode 15. In this method, before said insulating film 14 is formed, a sulfur passivation treatment is executed to the surface of the substrate 11, and said insulating film 14 is formed by an ECR-CVD method. For example, an n-type GaAs layer 12 and an n+ type Gaps layer 13 are formed sequentially on a p- type GaAs substrate 11 by an OMVPE method, the n+ GaAs layer 13 in a channel region is etched selectively and the n-type GaAs layer 12 is exposed. Then, a passivation treatment is executed by using an (NH4)2Sx solution; after that, an insulating film 14 such as SiN is formed by an ECR-CVD method; then, an annealing operation is executed at 380 to 520°C; after that, a gate electrode 15 is formed.


Inventors:
SHIKADA SHINICHI
Application Number:
JP20453190A
Publication Date:
March 24, 1992
Filing Date:
August 01, 1990
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H01L29/78; H01L21/31; H01L21/314; (IPC1-7): H01L21/31; H01L21/314; H01L29/784
Attorney, Agent or Firm:
Yoshiki Hasegawa (3 outside)



 
Next Patent: JPS491437