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Patent Searching and Data


Title:
FORMATION OF MULTILAYER WIRING FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH07122640
Kind Code:
A
Abstract:

PURPOSE: To provide a method for forming a multilayer wiring while protecting an interlayer insulation film, a barrier metal layer itself, etc., against crack at the time of high temperature sputtering.

CONSTITUTION: The method for forming a multilayer wiring in a semiconductor device, where a lower wiring layer 14 and an upper wiring layer 22 are connected through a contact hole 16 made through an insulation film 18 deposited on the lower wiring layer 14, comprises a step for forming a barrier metal layer 20 at the bottom, the side wall and the shoulder parts of the contact hole 16, and a step for filling the contact hole with Al by high temperature sputtering or reflowing. This method suppresses cracking of the barrier metal itself, the insulation film, etc., when the contact hole is filled with Al.


Inventors:
KOSHIO KENJI
CHISHIMA KENJI
Application Number:
JP28765593A
Publication Date:
May 12, 1995
Filing Date:
October 22, 1993
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L21/28; H01L21/768; H01L23/522; (IPC1-7): H01L21/768; H01L21/28
Attorney, Agent or Firm:
Mitsuo Takahashi