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Patent Searching and Data


Title:
FORMATION OF SEMICONDUCTOR RESISTANCE LAYER
Document Type and Number:
Japanese Patent JPS6184856
Kind Code:
A
Abstract:

PURPOSE: To easily obtain the stable titled layer having a prescribed resistance value by the simplified manufacturing process by a method wherein the impurity concentration and the shape of a resistance layer are controlled with high accuracy by plasma irradiation with positive photosensitive resin.

CONSTITUTION: An insulation layer 4 made of an SiO2 film is formed on the semiconductor substrate 3 having a base region 1 and an emitter region 2. Next, a polycrystalline Si layer 5 is formed on the insulation layer 4. Then, ions are implanted to this Si layer 5. Activation is contrived by heat treatment applied to the impurity-implanted Si layer 5. Pre-treatment is carried out to the surface of the Si layer 5 with CF4 plasma 7, thus setting the seat-resistance value close to the purposed value. A positive photosensitive resin layer 8 is formed on the Si layer 5. A positive mask pattern 9 is obtained by exposure. Thereafter, the titled layer 10 having the required shape and seat-resistance is obtained by etching the Si layer 5 with CF4 plasma, using the mask of the master pattern 9.


Inventors:
INOUE YOSHIAKI
Application Number:
JP20665184A
Publication Date:
April 30, 1986
Filing Date:
October 02, 1984
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/822; H01L27/04; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Takehiko Suzue