FORMING METHOD OF MULTILAYERED WIRING

Title:

FORMING METHOD OF MULTILAYERED WIRING

Document Type and Number:

Japanese Patent JPH0547941

Kind Code:

A

Abstract:

PURPOSE: To obtain the forming method of a multilayered wiring which can prevent the change of properties of wiring material which change is to be caused by contact of SOG with the wiring material like Al alloy, by a two-layered wiring using organic SOG.

CONSTITUTION: On a thermal oxide film 2 on a semiconductor substrate 1, an Al, alloy wiring 8 is formed, thereon a PSG film 3 and an SOG film 4 are formed in order, resist 5 is spread, the resist pattern of a via hole is formed by a photolithography process, the SOG in the via hole part is etched by wet etching, the resist 5 is eliminated, an SiN film 6 is formed, resist 5 is again formed, the resist pattern of a via hole is formed by a photolithgraphy process, the SiN film 6 and the PSG film 3 are subjected to dry etching, the resist 5 is eliminated, a second layer metal film is formed, and a two-layered wiring is formed by patterning.

Inventors:

TANAKA HISASHI

Application Number:

JP23097291A

Publication Date:

February 26, 1993

Filing Date:

August 19, 1991

Export Citation:

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Assignee:

CLARION CO LTD

International Classes:

H01L21/283; H01L21/302; H01L21/3065; H01L21/316; H01L21/318; H01L21/768; H01L23/522; (IPC1-7): H01L21/283; H01L21/302; H01L21/316; H01L21/318; H01L21/90

Attorney, Agent or Firm:

Takesaburo Nagata

Next Patent: PRODUCTION OF OPTICAL DIFFUSIVE PLATE