Title:
抵抗変化型不揮発性記憶素子のフォーミング方法
Document Type and Number:
Japanese Patent JP4972238
Kind Code:
B2
Abstract:
In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.
Inventors:
Ken Kawai
Kazuhiko Shimakawa
Koji Katayama
Shunsaku Muraoka
Kazuhiko Shimakawa
Koji Katayama
Shunsaku Muraoka
Application Number:
JP2012504948A
Publication Date:
July 11, 2012
Filing Date:
September 28, 2011
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G11C13/00; H01L27/10; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2007226883A | 2007-09-06 | |||
| JP2007004873A | 2007-01-11 |
Foreign References:
| WO2008149484A1 | 2008-12-11 | |||
| WO2005059921A1 | 2005-06-30 |
Attorney, Agent or Firm:
Hiromori Arai