PURPOSE: To automatically adjust the timing of setup or hold violation at the time of dividing and mapping an FPGA circuit.

CONSTITUTION: A delay data file 12 is generated by timing analysis means 7 to 11, and the number of delay elements is calculated in accordance with the violation margin in a step 14, and a signal line to which a delay element will be inserted is deleted in a step 15, and the delay element is inserted together with a new signal line in a step 16. The first delay data file is used as a delay master file 13 and is converted to information of the difference from the next generated delay data file 12 to obtain a difference data file, thus managing the generation.