To provide a fractional frequency division PLL device capable of improving convenience by reducing the number of parameters to be set and simplifying a circuit, and a control method thereof.

For an initial period of an A cycle of a first frequency division signal fpr, a second frequency division signal fA is maintained at a high level and a third frequency division signal fB is maintained at a low level. A 3 modulus prescaler 13 has an (M+1) frequency division value. In the successive B cycle, the second frequency division signal fA is at a low level, and the third frequency division signal fB is at a high level. The 3 modulus prescaler 13 has an (M-1) frequency division value in the case of a negative value and an (M+1) frequency division value in the case of a positive value in accordance with a code of a pseudo random number outputted from a modulator 8. Thereafter, it has an M frequency division. A comparison frequency divider 4 can obtain a frequency division value of (MN+A+Bx) including a pseudo random number Bx. A pseudo random number including a negative value can be used as it is to achieve fractional frequency division by modulation.