To reduce fractional sprious contained in an output signal less than a conventional example and to accelerate lock operation concerning a fractional N frequency synthesizer capable of sending the output signal of a frequency, which is the rational number multiple of a reference signal.

A frequency divider 9 is controlled to adopt N and (N+1) as a frequency dividing number and even when the phase error of a compare signal Sp is delayed or advanced, timing to set the frequency dividing number of the frequency divider 9 to (N+1) can occur. At the same time, when sucking a current from the side of a low-pass filter(LPF) 6 to a charge pump circuit 5, a current ISCH is discharged from a sprious cancel circuit 15 to the side of the LPF 6 and when discharging a current from the charge pump circuit 5 to the side of the LPF 6, a current ISCL is taken in from the side of the LPF 7 to the sprious cancel circuit 15.