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Patent Searching and Data


Title:
FRAME BUFFER MEMORY, GRAPHICS SUBSYSTEM, COMPUTER SYSTEM AND PIXEL ACCESS METHOD
Document Type and Number:
Japanese Patent JPH0855237
Kind Code:
A
Abstract:

PURPOSE: To provide a system which primarily performs the writing for a fast rendering operation by applying a graphics subsystem which includes a rendering controller and a frame buffer device containing a pixel ALU.

CONSTITUTION: A graphic subsystem 86 consists of the FBRAM(frame buffer random access memories) 71 to 82, a rendering controller 70 and a video output device 84. Each chip of FBRAM 71 to 82 has a pixel ALU including a circuit which generates the blend pixel value of both new and old pixel value and gives an interface to the controller 70 to primarily perform the writing. The controller 70 writes the pixel data into the FBRAM chips 71 to 82 via a rendering bus 98, and these FBRAM chips 71 to 82 transfer the video data to a video output circuit 84 via the video buses 134 to 137.


Inventors:
MAIKERU EFU DEARINGU
SUTEIIBUN EI SHIYARATSUPU
MAIKERU JII RABUERU
Application Number:
JP13264895A
Publication Date:
February 27, 1996
Filing Date:
May 08, 1995
Export Citation:
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Assignee:
SUN MICROSYSTEMS INC
International Classes:
G06T11/00; G06T15/00; G09G5/39; G09G5/399; G06T1/60; (IPC1-7): G06T15/40; G06T1/60; G06T11/00
Attorney, Agent or Firm:
Masaki Yamakawa