To easily disassemble fixed length frame format data at a high speed with a simple configuration.

Every time a frame 18 is received, a component corresponding reception clock generating circuit 12 counts a reception clock 14 at the start of reception time to obtain frame component corresponding reception clocks 16, 17. A component separate extract circuit 13 extracts each frame component at a high speed in a disassembled state based on the reception clocks 16, 17.