Title:
FRAME ERASE AND CORRECTION METHOD
Document Type and Number:
Japanese Patent JPH08293888
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To update a memory table even when frame continuous elimination occurs by using a delta for storing the difference of pitch delay between a prescribed frame and a frame preceding only by the several known number of frame. SOLUTION: A communication signal X(i) is supplied through a speech coder 20 which is the same as a conventional manner to an MUX 24 and a logic circuit 22. The output signal of the logic circuit 22 is the function of a present value [Pi (Tn )] of a parameter Pi applied in a time interval Tn and a value [Pi (Tn-m )] before the same Pi applied in a timer interval Tn-m , and (m) and (n) are integers. Therefore, the logic circuit 22 executes a function F indicated by D'j =F(Dj )= f(Pi Tn )+g(Pi Tn-m )}. In this case, j<=i is established. Plural bits indicated by D'j are multiplied and deformed by an MUX 24 with plural bits indicated by Di , and transmitted by radio through a communication channel 129. A received signal is processed by a DEMUX 30, and Di and D'j are restored, and the original signal X(i) is re-constituted by a communication decoder 35.
Inventors:
DOROA NAFUMI
Application Number:
JP5069096A
Publication Date:
November 05, 1996
Filing Date:
March 08, 1996
Export Citation:
Assignee:
AT & T CORP
International Classes:
H04L1/00; G10L19/00; (IPC1-7): H04L12/56; H04L1/00
Attorney, Agent or Firm:
Masao Okabe (2 outside)
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