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Title:
FRAME SYNCHRONIZATION DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH04332232
Kind Code:
A
Abstract:

PURPOSE: To shorten time for completing multiframe synchronization of input data that particular bits of each frame become a synchronous signal for every N (N; integer) frames (one multiframe).

CONSTITUTION: An extract circuit 3 for extracting specified bits for 2×N frames and a register 4 for storing the particular bits are installed in the frame synchronization detecting circuit. Further, a comparator 5 that compares bits themselves separated by the distance equivalent to N frames regarding particular bits stored in the register 4 and a counter 6 for detecting the synchronous signal based on the result of comparison. In this case, when a counted value by the counter 6 reaches a predetermined value, the bit and synchronous signal can be specified and it is considered that multiframe synchronization has been completed.


Inventors:
MIKAMI YASUSHI
Application Number:
JP13190791A
Publication Date:
November 19, 1992
Filing Date:
May 08, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J3/06; H04L7/08; H04Q3/42; (IPC1-7): H04J3/06; H04L7/08; H04Q3/42
Attorney, Agent or Firm:
Nobu Yanagikawa



 
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