PURPOSE: To reduce a time from the start of hunting till establishment of frame synchronization by providing plural frame synchronization bits so as to implement hunting through the use of pattern matching.

CONSTITUTION: A pattern matching establishing information bit 3 is inputted to one input terminal of an Ex-OR gate 4, and an output of the Ex-OR gate 4 is inputted to a shift register in 256-bit length and its output is inputted to the other input terminal of the Ex-OR gate 4. The content of each register of the shift register 5 has consecutive 1s while alternate 1, 0 at an interval of 256-bits is consecutive in the pattern matching establishing information bit 3. A 256-th bit of a consecutive pattern match valid flag 6 is set and fed to a frame synchronization establishment discrimination circuit 7 and when one bit in the 256 bits is set, the bit location is discriminated to be a frame synchronization location to establish the frame synchronization of the input data series 1. Thus, the time from the start of hunting till establishment of frame synchronization is reduced.