To provide a frame synchronizing detecting circuit where a memory capacity to store coincidence/dissidence information of a synchronizing pattern is decreased and a low access speed to a memory is attained.

The frame synchronizing detecting circuit 10 consists of a serial parallel conversion section 1 that converts serial data into parallel data, a register 2, a pattern detection section 3, a frame detecting processing section 4 and an information storage section 5. Thus, only presence of coincidence of a synchronizing pattern in a retrieved block and position information of coincidence detection are stored without storing coincidence/dissidence information of all bits for each frame.