Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FRAME SYNCHRONIZING SIGNAL DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS62150947
Kind Code:
A
Abstract:

PURPOSE: To prevent a pseudo synchronization by adopting a constitution that a gate is closed when a non-signal state is discriminated so as to make violation from a decoding circuit ineffective.

CONSTITUTION: A decoding circuit 1 outputs an NRZ code and a frame synchronizing signal. A non-signal state discrimination circuit discriminates whether or not a non-signal state exists from the CMI code input and outputs the discrimination result. A synchronization protection circuit 2 detects a fame synchronizing signal gated by a gate circuit 4 and confirms violation, and outputs a synchronization establishing display signal. The CMI code input is supervised at every prescribed period and when a non-signal state discrimination circuit 3 discriminates the absence of non-signal, the gate circuit is opened to make a frame period signal of the decoding circuit 1 effective and when the presence of non-signal is discriminated, the gate circuit is closed to make the violation from the decoding circuit ineffective thereby preventing the pseudo synchronization.


Inventors:
WAKAMORI MASAHIRO
Application Number:
JP29165985A
Publication Date:
July 04, 1987
Filing Date:
December 24, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04J3/06; H04L7/00; H04L7/08; (IPC1-7): H04L7/00; H04L7/08
Attorney, Agent or Firm:
Toshio Nakao



 
Previous Patent: JPS62150946

Next Patent: BUS FAULTY PART DETECTION SYSTEM