To provide a frame synchronous circuit which can inexpensively and securely execute synchronization without a large circuit scale.

A first synchronizing signal detection circuit 110 detects a first synchronizing signal from received data and a second synchronizing signal detection circuit 120 detects a second synchronizing signal. An error detection circuit 130 detects the error of received data. A synchronism protection circuit 140 controls the state of frame synchronism based on detection results by the first and second synchronizing signal detection circuits 110 and 120 and an error detection result by the error detection circuit 130. Thus, high speed and secure frame synchronism is realized.