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Title:
FRAME SYNCHRONOUS CIRCUIT
Document Type and Number:
Japanese Patent JPS5362921
Kind Code:
A
Abstract:

PURPOSE: To prevent the phase from being corrected mistakenly by providing a circuit which resets the counter by the first detection signal and allowing only the detection signal occurring within a position where the count value of the counter has ±n-bit centering on "0" to pass through NAND gate.


Inventors:
OGASAWARA MASANORI
SEKIKAWA TATSUAKI
Application Number:
JP13778476A
Publication Date:
June 05, 1978
Filing Date:
November 18, 1976
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H04J3/06; H04B7/26; H04L7/00; H04L7/08; H04Q11/04; (IPC1-7): H04J3/06