PURPOSE: To frequency-divide an input signal to convert it to an output signal whose frequency is 1/5 of the frequency of the input signal and to generate the output signal whose duty factor is 1: 1.

CONSTITUTION: An inverter 41 inverts an input signal and the result is inputted to the clock input of DFFs 13, 14. A buffer 31 receives the input signal to use it as a clock input of DFFs 11, 12 for the output of a delay time equal to the delay in the inverter 41. An AND gate 21 ANDs the inverted output of the DFF 12 and an inverted output of the DFF 14 and uses the result as the data input of DFFs 11, 13. The DFF 15 receives the output of the AND gate 21 as its clock input and uses its own inverted output as the data input and outputs an output signal being 1/5 frequency division of the input signal.