Title:
周波数変換装置
Document Type and Number:
Japanese Patent JP5083884
Kind Code:
B2
Abstract:
A signal processing unit (2) processes a digital signal from an AD conversion unit (1). The signal processing unit (2) includes a filter unit (4) and a memory unit (5) for accumulating filter coefficient data. An FIR filter (40) and an FIR filter (41) constituting the filter unit (4) update a filter coefficient with data supplied from the memory unit (5) during one sampling cycle. The FIR filters have frequency components whose amplitudes independently fluctuate as the time elapses. The FIR filter (40) and the FIR filter (41) have a common amplitude fluctuation cycle but have phases different by 90 degrees. The filter unit (4) outputs a difference or a sum of the two FIR filters.
More Like This:
| WO/2001/003295 | FIR DECIMATION FILTER |
| JP2570874 | [Title of Invention] Decimator circuit |
Inventors:
Kaoru Tsubara
Kiryu Shogo
Kiryu Shogo
Application Number:
JP2007296469A
Publication Date:
November 28, 2012
Filing Date:
November 15, 2007
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
International Classes:
H03H17/06; G10L21/013; G10L21/0324; H03H17/00; H03H17/02
Other References:
板垣賢治、蘆原郁、堀内竜三、桐生 昭吾,櫛型フィルタと周波数変換器を用いたハウリング低減法のハードウェア実装,電子情報通信学会技術研究報告. EA,日本,一般社団法人電子情報通信学会 ,2007年11月30日,EA2007-91,p.31-36