Title:
周波数補正回路及びこれを用いた時計装置
Document Type and Number:
Japanese Patent JP5114218
Kind Code:
B2
Abstract:
In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.
Inventors:
▲高▼妻 真一
Application Number:
JP2008003063A
Publication Date:
January 09, 2013
Filing Date:
January 10, 2008
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K23/66
Domestic Patent References:
| JP2006047101A | ||||
| JP2005156449A | ||||
| JP2004301753A | ||||
| JP63070616A | ||||
| JP62231196A |
Attorney, Agent or Firm:
Kakimoto Yasunari
Aniya Setsuo
Toru Yui
Hitoshi Kiyono
Fukuoka Masahiro
Aniya Setsuo
Toru Yui
Hitoshi Kiyono
Fukuoka Masahiro