To reduce the number of times of rewriting of a non-volatile memory.
The frequency counter 1 is provided with a binary counter part 11 having a binary counter 20 for counting-up frequency data and an EEPROM counter part 12 having an EEPROM 40 for storing the frequency data. In frequency count processing, the frequency data of the EEPROM 40 are loaded through a data bus L1 in the binary counter 20 and the binary counter 20 counts up the loaded frequency data by the prescribed frequency. Then, the counted-up frequency data are written through the data bus L1 in the EEPROM 40 and the frequency data of the EEPROM 40 are updated. The frequency is counted up in the binary counter 20 so that the rewriting of the EEPROM 40 can be attained only once by one time of frequency count processing and the number of times of rewriting can be reduced.
| JPH0464994 | NON-VOLATILE SEMICONDUCTOR MEMORY |
| JPH02257498 | INTEGRATED CIRCUIT |
YAMAZAKI SEIICHI
ITO KEIICHI
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