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Title:
FREQUENCY DISTRIBUTION PREPARING CIRCUIT
Document Type and Number:
Japanese Patent JPH04205462
Kind Code:
A
Abstract:

PURPOSE: To prepare the frequency distribution of various combinations with the conditions of various combinations and to attain rapid processing by providing this frequency distribution preparing circuit with a means for preparing frequency distribution and a means for outputting a frequency distribution preparing request to the succeeding FPGA block to release a current block.

CONSTITUTION: A CPU 1 loads data necessary for the preparation of frequency distribution from an auxiliary storage device 7 to a list memory 3. Then the CPU 1 clears the contents of a frequency distribution memory 4, sets up plural optional forming conditions in a mask memory 5, reads out logical circuit connecting information for preparing necessary frequency distribution from a program memory 2, and loads the information to respective FPGA blocks 11 to 14. Since the CPU 1 holds plural logical circuit connecting information, the frequency distribution of various combinations can rapidly be prepared by reloading these information on the CPU 1 during the operation of the system without changing hardware. Thus the frequency distribution of various combinations with the preparing conditions of various combinations can be prepared.


Inventors:
NISHIMURA MICHIO
Application Number:
JP33716490A
Publication Date:
July 27, 1992
Filing Date:
November 30, 1990
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F17/18; (IPC1-7): G06F15/36
Attorney, Agent or Firm:
Nakamura Shigenobu