To provide a frequency divider circuit and a counter circuit that can attain reduction of a test time without lowering an original circuit function in the frequency divider circuit and the counter circuit composed of flip-flop circuits connected in plural steps.

These devices are composed by connecting flip-flop circuits 1 to 4 in plural steps so that selector circuits 13 to 15 which selectively output signals from an FF circuit 1 (2 and 3) on the front step, and a clock signal from a clock signal terminal 6 to a clock terminal of an FF circuit 2 (3 and 4) on a rear step are intervened between the FF circuits 1 to 4 on each step and, furthermore, a test signal for giving priority to the clock signal is inputted to each of the selector circuits 13 to 15.