To provide a frequency divider circuit that can extend a variable range of overall circuit division ratio without increasing circuit scale and power consumption.
The frequency divider circuit includes: a variable frequency divider (2) for frequency-dividing a periodic signal (s5) at two division ratios and outputting a first frequency-divided signal (c1); a counter circuit (3) for outputting a count value (c2) of the number of cycles of the first frequency-divided signal (c1) and, when reset, restarting the counting action from an initial value; a comparator (4) for outputting as a second frequency-divided signal and supplying to the variable frequency divider (2) as a division ratio switching signal a pulse signal (s1) having High and Low inverted every time the count value (c2) matches a comparison reference value (a), and for outputting a reset signal (r) to the counter circuit (3) every time the count value (c2) matches the comparison reference value (a); and a control circuit (5) for supplying the comparison reference value (a) to the comparator (4).
TAGUCHI SHIGEYA
JPS58129833A | 1983-08-03 | |||
JPS52108762A | 1977-09-12 | |||
JP2008160353A | 2008-07-10 | |||
JPH06326605A | 1994-11-25 | |||
JPH07111452A | 1995-04-25 | |||
JPH0483425A | 1992-03-17 | |||
JP2003087113A | 2003-03-20 |
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