To provide a frequency-divider circuit capable of balancing improvement of stability of circuit operation with reduction of power consumption, and to provide a semiconductor device.
This frequency-divider circuit: includes an FF circuit 10 located on an anterior stage side close to an oscillation circuit and operating at a high frequency, and an FF circuit 10 located on a posterior stage side distant from the oscillation circuit and operating at a low frequency, wherein the respective FF circuits 10 at the anterior and posterior stages have each FB-SOI-MOSFETs 11-14, 21, 25 normally repeating turning on/off in operation of the frequency-divider circuit; and are set to satisfy |Vth1|<|Vth2|, when an absolute value of a threshold voltage of the MOSFETs 11-14, 21, 25 possessed by each FF circuit 10 at the anterior stage and that of the MOSFETs 11-14, 21, 25 possessed by each FF circuit 10 at the posterior stage are denoted by |Vth1| and |Vth2|, respectively.
Yoshiaki Naito
Yasuhiro Bono