To reduce the power consumption and a required number of FF circuits.

The frequency divider circuit is provided with: a high speed frequency divider circuit 11 comprising a high speed operating device, applying 1/M frequency division to a frequency of an input clock CLK1 into a frequency of a clock CLK2, and providing an output; and a low speed frequency divider circuit 12 comprising a low speed operating device, applying 1/N frequency division to the frequency of the clock CLK2 into a frequency of a clock CLK3, and providing an output. Both first and second circuits 11, 12 apply 1/(M×N) frequency division to the frequency of the input clock CLK1.