Title:
FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JP2555978
Kind Code:
B2
Abstract:
PURPOSE: To provide an odd number frequency divider circuit simple in circuit configuration, easy to change a frequency division ratio and capable of obtaining the output of duty factor of 50%.
CONSTITUTION: A master clock noninverting signal is given to each clock input CIN of odd number stages of flip-flops 11 of 2N-sets each in which data output Q of a pre-stage are given to a data input D of a post-stage and a data inverting output QB at a final stage is given to a data input D of a 1st stage and a master clock inverting signal is given to even number stages of flip-flops to form N-stages of Jhonson counters. Each data output of an N-th stage flip- flop and a 2N-th stage of flip-flop is given to an AND gate 13 and each data inverting output is given to an AND gate 14, in which data are ANDed. When the ANDed data are given to an OR gate 15, an output signal whose duty factor is 50% resulting from applying 1/N frequency division to a master clock is obtained.
Inventors:
YAMAMOTO NAONOBU
Application Number:
JP11487994A
Publication Date:
November 20, 1996
Filing Date:
May 27, 1994
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K23/48; H03K23/54; H03K23/64; H03K23/70; (IPC1-7): H03K23/48; H03K23/54; H03K23/64
Domestic Patent References:
| JP6388919A | ||||
| JP52134363A |
Attorney, Agent or Firm:
Yosuke Goto (2 outside)