PURPOSE: To suppress a rising time or falling time delay of a frequency division output with respect to an input clock signal by driving a level setting section based on a control signal and an output of a delay section at the rise and fall of an input signal so as to set an output node level to an input signal level.

CONSTITUTION: A frequency of a clock signal CLK of a noninverting output of an input signal is divided into 1/2 by the toggle operation of a D-FF 21 of a frequency divider section and a frequency division output of a noninverting output B is outputted. The Q output of the FF 21 is applied to a D-FF 42 of a control signal 40 receiving an inverting clock via an inverter 41. Then transistors(TRs) 61, 62 of a level setting section 60 are turned on by each of the Q output of the FF 21 and an inverse of Q output of the FF 42 and a level of the noninverting outputs A, B is made the same via a node N2. Thus, a time delay of the rise or the fall of a frequency division output with respect to the input clock signal is suppressed and the timing setting when both the clock signal and the frequency-divided clock signal are used as the clock signals is easily an surely implemented.