PURPOSE: To prevent a frequency-divided clock from being delayed behind an original clock even if the number of frequency-dividing stages is increased by setting an output signal to a first or a second level by the frequency-divided output of the corresponding frequency-dividing stage according to the level of said frequency-divided output as making the changing point of the original clock a trigger.

CONSTITUTION: The clock 21 of the output of a reset/set flip flop 35 varies as being delayed by the half period portion of the original clock 1 behind the clock 20. Accordingly when the clock 21 varies, the state of a point (a) is always stable, and response time required for a timing correction circuit 29 to vary as making the fall of the original clock 1 (rise of clock 50) the trigger becomes the delay time of the clock 21 behind the original clock 1. All the delay times of the rises or the falls of the clock 21 of the bi-divied clock of the original clock 1, the clock 41 of the quadri-divided clock and the clock 81 of the oct-divided clock behind the original clock 1 are equal in this way. Thus, even if the number of the frequency-dividing stages is increased, the delay time can be made not to be accumulated.