PURPOSE: To divide the frequency of an input signal, to convert the signal to an output signal having a 1/7 frequency and to generate the output signal with a 1:1 duty ratio.

CONSTITUTION: An inverter 31 inverts the input signal and defines it as the clock input of DFF 11 and 12. A buffer 41 receives the input signal and defines the output of delay time equal to that of the inverter 31 as the clock input of DFF 13 and 14. The DFF 11 and 12 and the DFF 13 and 14 respectively constitutes shift registers, and an AND gate 21 ANDs the inverted output of the DFF 12 and the inverted output of the DFF 14 and defines the result as the data input of the DFF 11 and 13. A DFF 15 defines the output of the AND gate 21 as the clock input, defines the own inverted output as the data input and outputs the output signal having the 1/7 input signal frequency.