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Title:
FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH0470121
Kind Code:
A
Abstract:

PURPOSE: To speed up the operation of the circuit and to reduce energy consumption by replacing a D-latch, which does not require a reset means, with a D-latch having two-input OR function.

CONSTITUTION: Since the inverted output of a D-latch 14 is turned to a high level in a reset state, an input to a D-latch 11 is set at the high level even when the output of a D-latch 16 is in any state, and since there is no influence upon operations, the reset means is not required for the slave latch of a flip-flop circuit in the final step. Then, the function of a multiple input OR circuit is allocated again to a transistor allocated to the reset means of this slave latch, and the two-input OR circuit is taken into the D-latch without increasing the number of serially connected gate logic stages. Thus, an area to be occupied by the circuit can be reduced, and current consumption can be lowered.


Inventors:
HIRAKATA NOBUYUKI
Application Number:
JP18245990A
Publication Date:
March 05, 1992
Filing Date:
July 10, 1990
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Yoshiki Hasegawa (3 outside)



 
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