PURPOSE: To provide the frequency divider circuit able to frequency-divide a frequency of an input signal into 1/10 or 1/11 in which a delay margin is larger than that of a conventional frequency divider circuit and malfunction at changeover of a frequency division ratio is suppressed.

CONSTITUTION: An input signal is given from an input terminal 9 to a CL input terminal of D flip-flop circuits 4, 5, 6. NAND circuits 1, 3 and a NOR circuit 2 give a switching signal given to a changeover terminal 8 and a signal based on an output of the D flip-flop circuits 5, 6 and an output of a T flip-flop circuit 7 to a D flip-flop circuit 4. An output of the D flip-flop circuit 4 is given to the T flip-flop circuit 7. Thus, even when a high frequency signal whose frequency exceeds 1GHz is received, the malfunction at changeover of a frequency division ratio is suppressed.