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Title:
1/11 FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH0529925
Kind Code:
A
Abstract:

PURPOSE: To obtain an output signal having a duty ratio equal to that of an input signal by dividing the frequency of the input signal to 1/11.

CONSTITUTION: D flip-flops 11, 12, 13 form a shift register A and use an input signal (a) as a drive source. D flip-flops 14, 15, 16 form a shift register B and use an inverse of the input signal (a) as a drive source. An output signal of an AND gate 18 receiving each inverting output signal of the D flip-flops 13, 16 is fed to the shift registers A, B. The period of the output signal of the AND gate 18 is a multiple of 11/2 of the period of the input signal (a). A DFF 17 formed to divide an output signal frequency of the AND gate 18 into 1/2 is used to obtain an output signal (b) whose duty ratio is equal to that of the input signal (a) and subject to 1/11 frequency division.


Inventors:
YANAKA TAKESHI
Application Number:
JP18663091A
Publication Date:
February 05, 1993
Filing Date:
July 25, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Umeo Yamauchi



 
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