PURPOSE: To facilitate high speed processing of the frequency divider circuit by reducing a delay time more in the frequency divider circuit required for a frequency division signal.

CONSTITUTION: A clock CLK is inputted to a gate terminal of a transmission gate T1 and an element S1 having an inverting amplification with a delay is connected between an output terminal and an input terminal of the transmission gate T1. That is, the delay time for the frequency division signal in the frequency divider circuit is more reduced by adopting the configuration of only one transmission gate T1, a single phase clock signal and the element S1 having a function of inverse delay amplification to facilitate the high speed processing of the frequency divider circuit.