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Patent Searching and Data


Title:
FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH08204545
Kind Code:
A
Abstract:

PURPOSE: To reduce the total power consumption by using a witch so as to apply a DC level to an input terminal of a 1st stage frequency divider circuit thereby stopping the frequency division operation when an output signal from an oscillator is selected.

CONSTITUTION: When a multiplexer MUX 20 uses a frequency fosc of an oscillator 10 as an output signal fout, a DC level is fed to an input terminal of a frequency divider 12 by a switch 26 to stop the operation of frequency dividers 12, 14, 16, 18 thereby reducing the power consumption. Furthermore, when any of outputs fosc/2-fosc/16 of specific frequency dividers is used for an output signal fout to select the MUX 20, a 2nd contact of a switch provided to a pre-stage of the specific frequency dividers 12, 14, 16, 18 is connected to a 2nd point, an output signal from the oscillator 10 or a signal frequency-dividing the signal is fed to the frequency divider. Then the 3rd point of the switch just after the selected frequency divider connects to ground and a DC level is applied to the frequency divider just after, then the frequency division of the frequency divider of a post stage is stopped. Thus, the power consumption for the overall operation is reduced.


Inventors:
SATO NORIHIKO
Application Number:
JP3296195A
Publication Date:
August 09, 1996
Filing Date:
January 30, 1995
Export Citation:
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Assignee:
SONY TEKTRONIX CORP
International Classes:
H03K23/64; H03B19/00; H03L7/06; (IPC1-7): H03K23/64; H03B19/00; H03L7/06