PURPOSE: To obtain a sure-operation frequency divider by resetting FF in each stage required for counting n-1 by a sufficiently resettable pulse in a 1/n frequency divider circuit dependent upon an asynchronous counter.
CONSTITUTION: Clock pulse A of frequency f0 is inputted to terminal 7 of asynchronous counter 12; and for example, in case of n=7, when counter 12 constituted by T-FF 8, 9 and 10 counts 6, output E of NAND gate 11 becomes L. Then, D-FF where clock inversion A anti-phase to clock A and output E of gate 11 are inputted to the CL terminal and the D terminal respectively resets FF 8, 9 and 10 during one cycle of clock inversion A. As a result, a period corresponding to seven clocks A can be obtained at output D of FF 10, and a required frequency division is performed, and further, a reset pulse corresponding to one cycle of clock A is obtained to make operation sure.
| JP2004289422 | FREQUENCY DIVIDER CIRCUIT |
YABU TOSHIOMI
YAMADA KOUICHI
YOSHINO TADASHI
| JPS5224458A | 1977-02-23 |